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PRELIMINARY DATA SHEET
MICRONAS
DAC 3560C Audio-Subsystem for Portable Applications
Edition Sept. 8, 2004 6251-588-2PD
MICRONAS
DAC 3560C
Contents Page 4 4 4 6 6 7 7 7 8 8 8 8 8 9 9 9 9 9 9 9 10 10 14 14 16 18 18 18 18 19 19 19 19 20 20 22 22 24 24 25 28 30 31 31 32 Section 1. 1.1. 1.2. 2. 2.1. 2.2. 2.3. 2.4. 2.5. 2.6. 2.7. 2.8. 2.9. 2.10. 2.11. 2.12. 2.13. 2.14. 2.15. 2.16. 3. 3.1. 4. 4.1. 4.2. 4.3. 4.3.1. 4.3.2. 4.3.3. 4.3.4. 4.3.5. 4.3.6. 4.3.7. 4.4. 4.5. 4.6. 4.6.1. 4.6.2. 4.6.2.1. 4.6.3. 4.6.4. 4.6.5. 4.6.6. 4.6.6.1. 4.6.6.2. Title Introduction Features Target Systems Functional Description Digital Audio Interface (I2S) Clock System Control Interface Registers I2C Bus Interface SPI Bus Interface Noise Shaper and Multibit DAC Analog Low-Pass Filter Analog Input Analog Audio Driver Output LDO Charge Pump Reference Block Temperature Overload Protection Power Management Click and Pop Suppression Control Registers Register Map Specifications Outline Dimensions Pin Connections and Short Descriptions Pin Descriptions Power Supply Pins Exposed Die Pad Analog Reference Pins Analog Audio Pins Digital Audio Input Pins Control Interface Pins Other Pins Pin Configurations Pin Circuits Electrical Characteristics Absolute Maximum Ratings Recommended Operating Conditions General Recommended Operating Conditions Characteristics (LDO Mode) Characteristics (Non-LDO Mode) Terminology Digital Characteristics I2C Bus Characteristics I2S Bus Characteristics
PRELIMINARY DATA SHEET
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DAC 3560C
Contents, continued Page 33 33 34 35 36 36 36 37 38 38 39 40 42 Section 4.6.6.3. 4.6.6.4. 4.6.6.5. 4.6.7. 5. 5.1. 5.2. 5.3. 5.3.1. 5.3.2. 6. 6.1. 7. Title Reset Input Characteristics Mode Input Characteristics SPI-Bus Characteristics Power Consumption (LDO Mode) Detailed Mode Description LDO Mode, Using the internal Low-Dropout Regulator Non-LDO Mode, Using the DAC 3560C without the LDO Headphone Common Driver Digital Supply Power On/Off Sequence Application Circuit Suggestions for System Debugging Data Sheet History
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Audio-Subsystem for Portable Applications Release Note: Revision bars indicate significant changes to the previous edition. This document is valid for version B1 and following versions. 1.1. Features
PRELIMINARY DATA SHEET
- Three integrated short-circuit-protected power audio drivers are provided: 1. Stereo headphone output (25 mW at VSUP =2.85 V, or 80 mW at VSUP =5 V respectively) 2. Mono earpiece output (100 mW at VSUP =2.85 V, or 300 mW at VSUP =5 V, respectively) 3. Mono loudspeaker output (400 mW at VSUP =3 V, or 1.1 W at VSUP =5 V, respectively) - integrated LDO (Low Drop-Out Regulator) - 100 dB PSRR - 98 dB (A) dynamic range multibit Sigma Delta DAC - continuous sample rates from 8 kHz to 192 kHz - capacitor-free headset connection - analog stereo and mono line inputs with programmable gain - I2C/SPI-compatible serial control ports - I2S digital audio interface - programmable power management - -30 dB to 6 dB analog volume, mute - 2.2 V to 5.5 V supply voltage - 1.8 V to 5.5 V digital I/O voltage - standby mode - zero-power mode (< 10 A) - PQFN40-1 and PMQFP44-1 packages
1. Introduction The DAC 3560C is a single-chip, high-precision, dual digital-to-analog converter designed for audio applications. The employed conversion technique is based on oversampling with noise-shaping. With Micronas' unique multibit sigma-delta technique, less sensitivity to clock jitter, high linearity, and a superior S/N ratio have been achieved. The DAC 3560C is controlled via SPI or I2C bus. Digital audio input data is received via a versatile I S interface. The DAC 3560C provides three integrated power audio drivers: a stereo headphone, a mono earpiece and a mono loudspeaker driver. Moreover, mixing additional analog sources to the D/A-converted signal is supported. For applications with a noise-critical power supply environment, the DAC 3560C is equipped with an integrated low drop-out voltage regulator (LDO). The LDO provides a stable 2.85 V output voltage and is intended for supplying the headphone and earpiece drivers. With the LDO, the power supply rejection ratio (PSRR) of the audio outputs is improved to more than 100 dB. The DAC 3560C is designed for all kinds of applications in the audio and multimedia field, such as mobile phones, PDAs, and digital audio players.
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1.2. Target Systems - PDAs - hand-held terminals - mobile and cordless phones - portable MP3 and CD players
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DAC 3560C
VLDO (AVDD)
VBAT
CPIN
PVDD
SREF CF SGND
Reference Block
LDO
Charge Pump
-30 dB ... 6 dB, mute -20 dB ... 20 dB, mute
LSVDD
LSP LSN
AUXL
-20 dB ... 20 dB, mute
LSVSS1
x0.5
AUXR
LSVSS2
-20 dB ... 20 dB, mute AIN
-30 dB ... 6 dB, mute
EPVDD
x0.5
EPP EPN
DVDD
IOVDD
Mono PLL
Stereo mode
Mono mode
EPVSS1 EPVSS2
x0.5
Stereo
RES
-30 dB ... 6 dB, mute HPVDD
DAC DAI W SI CLI Digital Audio Interface
Left Channel
HPL
DAC
-30 dB ... 6 dB, mute Mono Right Channel Stereo HPR
SDO SDI CS SCLK
I2C/SPI I2C/SPI
Control Interface
Temperature Overload Protection
1
HPCM
HPVSS
MODE
DVSS
AVSS
Fig. 1-1: Block diagram
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2. Functional Description The main blocks are described in the following chapters. All functions are controlled via I2C/SPI protocol. 2.1. Digital Audio Interface (I2S) The I2S interface is the digital audio interface between the DAC 3560C and external digital audio sources. It covers most of the I2S-compatible formats. All modes have two common features: 1. The MSB is left-justified to an I2S frame identification (WSI) transition. 2. Data is valid on the rising edge of the bit clock CLI. 16-bit mode: In this case, the bit clock is 32 x fsaudio. Maximum word length is 16 bit. 32-bit mode: In this case, the bit clock is 64 x fsaudio. Maximum word length is 32 bit.
PRELIMINARY DATA SHEET
Automatic Detection: No I2C/SPI control is required to switch between 16-bit and 32-bit mode. It is recommended to switch the DAC 3560C into mute position while alternating between the two modes. For high-quality audio, it is recommended to use the 32-bit mode of the I2S interface to make use of the full dynamic range (if more than 16 bits are available). Left-Right Selection: Standard I2S format defines an audio frame always starting with the left channel and low-state of WSI. However, the DAC 3560C permits changing the polarity of WSI. Delay Bit: The standard I2S format requires a delay of one clock cycle between transitions of WSI and data MSB. In order to fit other formats, however, this characteristic can be switched on or off. Note: Volume mute should be applied before changing I2S mode in order to avoid audible clicks
Vh
CLI
Vl
Vh
DAI
15 14 13 12 11 10 9 8
Vl
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
76543210
programmable delay bit
WSI
Vh Vl
left 16-bit audio sample
right 16-bit audio sample
Fig. 2-1: I2S 16-bit mode
Vh
CLI
Vl
Vh
DAI
31 30 29 28 27 26 25 24
Vl
7 6 5 4 3 2 1 0 31 30 29 28 27 26 25 24 7 6 5 4 3 2 1 0
programmable delay bit
WSI
Vh Vl
left 32-bit audio sample
right 32-bit audio sample
Fig. 2-2: I2S 32-bit mode
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PRELIMINARY DATA SHEET
DAC 3560C
2.4. Registers All registers of the DAC 3560C are 8 bits wide and offer read/write access. In Section 3. "Control Registers", a definition of the DAC 3560C control registers is shown. A hardware reset initializes all control registers to 0, which is the default value for all registers. The registers are addressed by the sub-address byte, which follows the device address in I2C mode and is the first byte to be sent in SPI mode. The structure of the sub-address is identical in both modes (R/W is ignored in I2C mode). Table 2-2: Sub-Address Byte
Bit
Function
2.2. Clock System Most DACs need 256 x fsaudio, 384 x fsaudio, or at least an asynchronous clock. The DAC 3560C does not need an external Master clock. No crystal is required. All internal clocks are generated by an internal PLL circuit, which locks to the I2S bit clock (CLI). If no I2S clock is available, the IC can still be controlled via I2C, SPI and the analog signal path is still available as no I2S clock is needed for this. The PLL generates the clock for the DAC and the noise shaping system. Audible oversampling artifacts even at low audio sampling frequencies are eliminated.
2.3. Control Interface The DAC 3560C has many register-programmable features. The control interface is used to program the registers of the device. It uses four pins:
D7
0
D6
0
D5
R/W
D4
A4
D3
A3
D2
A2
D1
A1
D0
A0
Table 2-3: Structure of the Sub-Address Byte SCLK - Serial Data Clock SDI - Serial Data Input (Input/Output for I2C) SDO - Serial Data Output (SPI) CS - Chip Select (SPI) Table 2-1: Standard Protocols MODE Pin 1 0 Control Protocol I2C SPI R R/W1) A [4:0]
1)
Reserved Read/Write Access Control Interface Sub-Address
Set to 0 1=Read 0=Write
R/W must be set to 0 in I2C mode
The control interface supports two standard protocols, the I2C protocol (two-wire operation) and the SPI protocol (three or four-wire operation). The state of the MODE pin selects the control interface type.
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DAC 3560C
2.5. I2C Bus Interface The DAC 3560C is equipped with an I2C bus slave interface. The I2C bus interface uses one level of subaddressing: the I2C device address is used to address the IC. The registers are readable and writable. The register address is incremented automatically at each data byte unless a stop condition occurs. The I2C device address is given below. Table 2-4: I2C device address byte A7 1 A6 0 A5 0 I2C A4 1 A3 1 A2 0 A1 1 W/R 0/1
SDO
PRELIMINARY DATA SHEET
contains the Register address. The following byte or bytes are then read/write register data. If more than one data byte appears without changing CS, the register address will be incremented automatically at each data byte.
CS
SCLK Sub-Adress Byte MSB LSB Data Bytes byte 1 high Z - - - byte n
SDI
bus protocols for write and read Fig. 2-3 shows operations of the interface; the read operations require an extra start condition and repetition of the chip address with the device read command (DR). Fields with signals/data originating from the DAC 3560C are marked with a gray background.
Fig. 2-4: SPI Control Port - Write Access
CS
SCLK
Example: I2C single write access
S DW A subaddress A data byte A P
SDI
Sub-Adress Byte MSB LSB
Ignored Data Bytes
Example:
S
I2C
single read access
A subaddress A S DR A data byte N P
DW
SDO
high Z byte 1 --byte n
Fig. 2-5: SPI Control Port - Read Access
SDI SCLK S 1 0 P
2.7. Noise Shaper and Multibit DAC The input signal is interpolated to a higher sampling rate. A successive noise shaper converts the oversampled audio signal into a multibit noise-shaped signal. This technique results in extremely low quantization noise in the audio band.
Fig. 2-3: Example of an I2C protocol for the DAC 3560C (MSB first; data must be stable while clock is high)
Abbreviations: A = Acknowledge N = Not Acknowledge (NAK) S = Start P = Stop DW = I2C Device Write Address (9Ahex) DR = I2C Device Read Address (9Bhex) 2.6. SPI Bus Interface The SPI bus is a 4-wire serial communications interface. Unlike the I2C bus, the SPI uses two separate pins for input and output and CS signal instead of individual device addresses. Read and write starts with a low signal at CS. The first byte is always interpreted as sub-address byte, which 2.8. Analog Low-Pass Filter The multibit DAC is followed by a third-order analog low-pass filter with a cut-off frequency of approximately 70 kHz. It removes the out-of-band components of the oversampled audio signal.
2.9. Analog Input In addition to the digital audio input, the DAC 3560C provides three analog inputs, (AUXL, AUXR, AIN) for stereo and mono signals. The analog audio signals can be mixed to the digital audio signal as well as being used without digital audio. All three analog inputs are equipped with 20 dB to -20 dB gain controls for individual input level adjustments in steps of 2 dB. They feature additional mute position.
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PRELIMINARY DATA SHEET
DAC 3560C
2.12. Charge Pump The DAC 3560C offers an internal charge pump circuit that allows to operate the IC with a supply voltage as low as 2.2 V. An additional capacitor must be connected between pin PVDD and pin VLDO for the charge pump to work properly. The switching frequency is far above the audio range and therefore does not interfere with the audio signals. The charge pump must be turned on if the supply voltage of the IC drops below 2.7 V. (see Section 5.) for details on using the DAC 3560C with a lowered supply voltage of 2.2 V.
2.10. Analog Audio Driver Output The device provides three integrated audio drivers. Table 2-5: Analog Audio Driver Output Integrated Audio Drivers Stereo headphone driver Mono earpiece driver Mono loudspeaker driver 25 mW at 2.85 V supply 80 mW at 5 V supply 100 mW at 2.85 V supply 300 mW at 5 V supply 400 mW at 3 V supply 1.1 W at 5 V supply
2.13. Reference Block This block provides the reference level for the analog audio signals. Two modes are possible:
All drivers are equipped with analog volume controls, which are individually adjustable from 6 dB to -30 dB in 1.5 dB steps and mute. The earpiece driver and the loudspeaker driver have differential outputs, while the headphone drivers are single-ended. Single-ended drivers usually require a large coupling capacitor to block the DC bias from the headphone. The DAC 3560C provides a headphone common output (HPCM), which eliminates the need for such bulky DCblocking capacitors. The headphone and earpiece drivers are short-circuit protected. The loudspeaker output pins are not short-circuit-proof.
LDO-Mode: The audio reference level is fixed to 1.425 V (Pin SREF), which is one half of the LDO output voltage. Non-LDO Mode: The audio reference level at Pin SREF is derived from an internal voltage divider to VBAT/2. A capacitor connected between SREF and SGND reduces the noise coming from SREF. In addition, a second capacitor can be connected to pin CF to form a second order noise filter. (See Section 5. for details).
2.11. LDO 2.14. Temperature Overload Protection For applications with a noise-critical power supply environment, the DAC 3560C is equipped with an integrated Low-Dropout Voltage Regulator (LDO). The LDO provides a stable 2.85 V output voltage and is intended to supply the headphone and earpiece drivers. With the LDO, the Power Supply Rejection Ratio (PSRR) of the audio outputs is improved to more than 100 dB. For applications where the LDO cannot be used, e.g., for supply voltages below 2.85 V, it can be disabled via the Mode-Control-Register, (see Section 5.) for details on using the DAC 3560C with or without the internal LDO. The LDO is short-circuit-protected. The DAC 3560C has an internal temperature overload protection, which disables all audio drivers and the LDO, if the junction temperature exceeds 145 C. Once the chip has cooled down to 130 C, the LDO and the audio drivers are enabled again.
2.15. Power Management As the device has more than one signal path, the DAC 3560C offers a block-control register, which permits individual control over the power state of the signal chain for optimized power consumption. A Zero Power and a Standby Mode are also provided.
2.16. Click and Pop Suppression The DAC 3560C has on-chip facilities allowing to turn the audio output drivers on or off without audible click and pop transients.
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3. Control Registers The DAC 3560C contains 11 registers (all 8 bits). All registers, with the exception of the Reset Register, (write only), allow read and write access. 3.1. Register Map
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Table 3-1: Register Map Table SubAddress Register Reset Register Block Control Register Mode Control Register I2S Interface Control Register Left Headphone Volume Control Right Headphone Volume Control Earpiece Volume Control Loudspeaker Volume Control Left Input Aux Gain Control Right Input Aux Gain Control Ain Input Gain Control Reserved
Note: The default value for all registers after software or hardware reset is 0.
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh...FFh
Table 3-2: Register Description Name SubAddress Dir Default after Reset Function
DACC-Register Reset Register Reset Block Control Register PDAC PAIN PAUX PL PE PRH PLH ENHPC h00 h0X h01 h01[7] h01[6] h01[5] h01[4] h01[3] h01[2] h01[1] h01[0] W W RW RW RW RW RW RW RW RW RW h00 0 h00 0 0 0 0 0 0 0 0 Writing to this register clears all internal registers to their default reset value Ignored, if in Standby or Zero Power Mode 1 = On, 0 = Off (Power DAC) 1 = On, 0 = Off (Power Ain) Gain 1 = On, 0 = Off (Power Aux) Gain 1 = On, 0 = Off (Power Loudspeaker) Driver 1 = On, 0 = Off (Power Earpiece) Driver 1 = On, 0 = Off (Power Right Headphone) Driver 1 = On, 0 = Off (Power Left Headphone) Driver 1 = On, 0 = Off (Enable Headphone Common Output) Driver
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DAC 3560C
Table 3-2: Register Description, continued Name SubAddress h02 h02[7] h02[6] h02[5] h02[4] h02[3] h02[2] h02[1:0] Dir Default after Reset h00 0 0 0 0 0 0 0 Function
Mode Control Register - RDWN CPON BYPLDO SNLDOM SMM PM
RW RW RW RW RW RW RW RW
For details, please refer to Section 5. Reserved 1 = On, 0 = Off (Ramp down SREF during Stand-by Mode) 1 = On, 0 = Off (Charge pump on, only in NON-LDO Mode) 1 = On, 0 = Off (Bypass LDO (only in Standby, Zero Power) 1 = On, 0 = Off (Select Non-LDO Mode) 1 = Mono, 0 = Stereo (Select Stereo or Mono Mode) PM[1:0] 00 Zero Power Mode 01 Standby Mode 11 Operating Mode 10 Reserved
I2S Interface Control Register - POL
h03
RW
h00
h03[7:5] h03[4]
RW RW
0 0
Reserved Invert Polarity of Word Strobe Input POL=0 - Left Channel WSI=0 POL=1 - Right Channel WSI=0
DEL SR
h03[3] h03[2:0]
RW RW
0 0
1 = Delay, 0 = no Delay (Delay Bit) SR[2:0] 000 32 kHz - 48 kHz 001 24 kHz - 32 kHz 010 16 kHz - 24 kHz 011 12 kHz - 16 kHz 100 8 kHz - 12 kHz 101 6 kHz - 8 kHz 110 96 kHz 111 192 kHz Sample Rate Sample Rate Sample Rate Sample Rate Sample Rate Sample Rate Sample Rate Sample Rate
Left Headphone Volume Register - LHV
h04
RW
h00
h04[7:5] h04[4:0]
RW RW
0 0
Reserved LHV[4:0] Left Headphone Volume 00000 00001 ----11001 11010-11111
Mute -30 dB in steps of 1.5 dB 6 dB 6 dB
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Table 3-2: Register Description, continued Name SubAddress h05 Dir Default after Reset h00 Function
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Right Headphone Volume Register - RHV
RW
h05[7:5] h05[4:0]
RW RW
0 0
Reserved RHV[4:0] Right Headphone Volume 00000 Mute 00001 -30 dB ----in steps of 1.5 dB 11001 6 dB 11010-11111 6 dB
Earpiece Volume Register - EV
h06
RW
h00
h06[7:5] h06[4:0]
RW RW
0 0
Reserved EV[4:0] Earpiece Volume 00000 00001 ----11001 11010-11111
Mute -30 dB in steps of 1.5 dB 6 dB 6 dB
Loudspeaker Volume Register - LV
h07
RW
h00
h07[7:5] h07[4:0]
RW RW
0 0
Reserved LV[4:0] Loudspeaker Volume 00000 00001 ----11001 11010-11111
Mute -30 dB in steps of 1.5 dB 6 dB 6 dB
Left Aux Gain Register - ALV
h08 h08[7:5] h08[4:0]
RW RW RW
h00 0 0 Reserved ALV[4:0] Left AUX Pre-Amplifier Gain 00000 Mute 00001 -20 dB ----in steps of 2 dB 10101 20 dB 10110-11111 20 dB
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Table 3-2: Register Description, continued Name SubAddress h09[7:5] h09[7:5] h09[4:0] Dir Default after Reset h00 0 0 Reserved ARV[4:0] Right AUX Pre-Amplifier Gain 00000 Mute 00001 -20 dB ----in steps of 2 dB 10101 20 dB 10110-11111 20 dB Function
Right AUX Gain Register - ARV
RW RW RW
AIN Gain Register - AIV
h0A[7:5] h0A[7:5] h0A[4:0]
RW RW RW
h00 0 0 Reserved AIV[4:0] AIN Pre-Amplifier Gain 00000 00001 ----10101 10110-11111
Mute -20 dB in steps of 2 dB 20 dB 20 dB
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DAC 3560C
4. Specifications 4.1. Outline Dimensions
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Fig. 4-1: PQFN40-1: Plastic Quad Flat Non-leaded package, 40 pins, 6 x 6 x 0.85 mm3, 0.5 mm pitch Ordering code: XN Weight approximately 0.1 g
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Fig. 4-2: PMQFP44-1: Plastic Metric Quad Flat Package, 44 leads, 10 x 10 x 2 mm3 Ordering code: QG Weight approximately 0.5 g
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4.2. Pin Connections and Short Descriptions NC = not connected LV = leave vacant IN = Input, OUT = Output, IN/OUT = Input/Output P = Power GND = Ground OBL = obligatory; connect as described in the circuit diagram Pin No.
PQFN 40-1 PMQFP 44-1
PRELIMINARY DATA SHEET
Pin Name
Type
Connection
(If not used)
Short Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
1 2 3 4 5 6 7 8 9 10 13 14 15 16 17 18 19 20
VBAT LSVSS1 LSP LSVDD LSN LSVSS2 DVDD DVSS MODE IOVDD SDI SCLK SDO CS DAI WSI CLI RES NC NC
P P OUT P OUT P P P IN P IN/OUT IN OUT IN IN IN IN IN
- GND LV VBAT LV GND - GND OBL - OBL OBL LV GND GND GND GND OBL NC NC
Power Supply Loudspeaker Driver Ground Loudspeaker Differential Positive Output Loudspeaker Power Supply Driver Loudspeaker Differential Negative Output Loudspeaker Driver Ground Digital Power Supply Digital Ground I2C / SPI Control Mode Selection Digital I/O Power Supply SPI / Data In (I2C Data In/Out) SPI / I2C CLK SPI / Data Out SPI Chip Select (active Low) I2S Data In I2S Word Strobe In I2S Clock In Reset Input (active Low) Not connected Not connected Analog Mono Input Analog AUX Input Left Channel Analog AUX Input Right Channel Headphone Common Output Headphone Driver Ground Headphone Output Left Channel
24 25 26 27 28 29
AIN AUXL AUXR HPCM HPVSS HPL
IN IN IN OUT P OUT
LV LV LV LV GND LV
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DAC 3560C
Pin No.
PQFN 40-1 PMQFP 44-1
Pin Name
Type
Connection
(If not used)
Short Description
27 28 29 30 31 32 33 34 35 36 37 38 39 40
30 31 32 33 34 35 36 37 38 39 40 41 42 43 11, 12, 21, 22, 23, 44
HPR HPVDD SGND SREF CF EPVSS2 EPN EPVDD EPP EPVSS1 AVSS PVDD CPIN VLDO (AVDD) NC
OUT P P OUT OUT P OUT P OUT P P OUT P P
LV VLDO GND OBL SREF GND LV VLDO LV GND GND VLDO OBL VBAT NC
Headphone Output Right Channel Headphone Driver Power Supply Ground for Audio Signal reference level, Connect to GND Audio Signal reference level Audio Signal reference level Earpiece Driver Ground Earpiece Differential Negative Output Earpiece Driver Power Supply Earpiece Differential Positive Output Earpiece Driver Ground Analog Ground Charge Pump Out Charge Pump In LDO Output, Analog Power Supply Not connected
Note: Pins CPIN, EPVDD, and HPVDD must be connected to Pin VLDO
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DAC 3560C
4.3. Pin Descriptions 4.3.1. Power Supply Pins The power supply pins are divided into functional regions: LDO region, digital region, digital input region, three analog regions. Two major applications are possible: LDO mode or Non-LDO mode. They are described in detail in Section 5.1. and Section 5.2. DVDD, IOVDD, DVSS (see Fig. 4-11, Fig. 4-12, Fig. 4-13, Fig. 4-16): - The DVDD pin supplies all internal digital parts of the DAC 3560C and the RES input. - The IOVDD pin supplies all digital inputs and outputs of the DAC 3560C, except the RES input. - DVSS is the ground connection for all digital circuits. AVSS, PVDD, CPIN (see Fig. 4-6): VBAT, VLDO (see Fig. 4-7): VBAT is the input of the internal LDO. VLDO is the output of the LDO. If the LDO function is not used, VBAT must be connected to VLDO. At PVDD an internal supply can be generated. Pin CPIN must be connected to VLDO. This function is necessary in Non-LDO mode and external power voltages below 2.7 V. At these low supply voltages, an internal charge pump ensures proper functioning of the chip down to 2.2 V. An external capacitor of 47 nF must be connected from PVDD to VLDO. AVSS serves as ground pin for the aforementioned capacitor and must be connected to DVSS. HPVDD, HPVSS (see Fig. 4-9, Fig. 4-10) The HPVDD and HPVSS pins supply the headphone drivers. HPVDD must be connected to VLDO. HPVSS must be connected to AVSS. EPVDD, EPVSS (see Fig. 4-14) The EPVDD and EPVSS pins supply the earpiece drivers. EPVDD must be connected to VLDO. EPVSS must be connected to AVSS. LSVDD, LSVSS (see Fig. 4-15) The LSVDD and LSVSS pins supply the loudspeaker drivers. LSVDD must be connected to VBAT. LSVSS must be connected to AVSS.
PRELIMINARY DATA SHEET
4.3.3. Analog Reference Pins SREF, CF (see Fig. 4-5): Reference for analog audio signals. SREF is used as reference for the internal op amps and drivers. There are two modes of usage: 1. LDO mode: SREF must be blocked against SGND with a 3.3 F (plus optional 10 nF) capacitor. CF must be connected to SREF. The internal reference is fixed at 1.425 V. 2. Non-LDO mode (ratiometric mode): a) SREF and CF are connected together. Both are blocked against SGND with a 3.3 F (+ optional 10 nF capacitor). The PSRR of SREF is reduced compared to the LDO Mode. b) SREF is blocked against SGND with a 1 F (+ optional 10 nF) capacitor and CF is blocked with a 1.0 F capacitor. PSRR is improved regarding "a)". The internal reference is VLDO/2.
Note: SREF can be used as reference input for external op amps, if no current load is applied. Keep the traces at SREF and CF as short as possible to avoid system noise pickup.
SGND (see Fig. 4-3): Reference ground for the internal voltage reference and biasing circuits. This pin should be connected to a clean ground potential. Any external distortions on this pin will affect the analog performance of the DAC 3560C. SGND must be connected to AVSS.
4.3.2. Exposed Die Pad The exposed die pad on the bottom side is electrically connected to the substrate of the chip. Leave it unconnected or connect it to a clean ground.
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PRELIMINARY DATA SHEET
DAC 3560C
4.3.5. Digital Audio Input Pins CLI, DAI , WSI (see Fig. 4-10): These three pins are inputs for the digital audio data DAI, frame indication signal WSI, and bit clock CLI. The digital audio data is transmitted in an I2S-compatible format. Audio word lengths of 16 and 32 bits are supported, as well as SONY and Philips I2S protocol. Do not leave these pins unconnected!
4.3.4. Analog Audio Pins AUXL, AUXR, AIN (see Fig. 4-8): These pins provide analog stereo/mono inputs. Auxiliary input signals, e.g. the output of a conventional receiver circuit or the output of a tape recorder can be connected here. The input gain is programmable between -20 dB and +20 dB in steps of 2 dB. The input signals have to be connected by capacitive coupling. Each signal can be mixed to the output of the embedded DAC. HPL, HPR, HPCM (see Fig. 4-9, Fig. 4-10): The HPL/R pins are connected to the internal headphone drivers. They can be used for single-ended stereo headphones of greater or equal than 16 Ohm. There are two modes of applying the load: 1. Load to ground: Each channel must be coupled capacitively. 2. Load to HPCM: Channels can be coupled directly to HPCM. The common mode buffer at HPCM must be enabled before activating the drivers. EPP, EPN (see Fig. 4-14): The EPP/N pins are connected to the internal earpiece driver. They can be used for differential mono earpiece speakers of greater than, or equal to, 16 Ohm. LSP, LSN (see Fig. 4-13): The LSP/N pins are connected to the internal loudspeaker driver. They can be used for differential mono loudspeakers of greater or equal than 4 Ohm. All analog outputs show a programmable gain range of -30 dB to +6 dB plus Mute.
4.3.6. Control Interface Pins SCLK, SDI, SDO, MODE, CS (see Fig. 4-10, Fig. 4-11, Fig. 4-12): Two protocol control modes are possible: 1. I2C mode: SCLK and SDI provide the connection to the serial control interface. 2. SPI mode: Two additional signals are needed: CS serves as the interface chip select. SDO sends out data after a read command. MODE toggles between the two control modes.
4.3.7. Other Pins RES (see Fig. 4-10): This pin may be used to reset the chip. After power-up it should be raised from DVSS potential to DVDD level. Signal function is active low.
Note: Any occurrence of a short circuit at pins HPL, HPR, HPCM, EPP, EPN may result in initialization of the built-in temperature protection unit, which turns off the output drivers. When the short-circuit condition is removed, the drivers will be turned on again. The pins LSP and LSN are not short-circuit-proof.
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DAC 3560C
4.4. Pin Configurations 4.5. Pin Circuits
PRELIMINARY DATA SHEET
HPL HPR HPVDD SGND SREF
HPVSS HPCM AUXR AUXL AIN
VLDO (AVDD) 90 k SREF CF
20 19 18 17 NC NC RES CLI WSI DAI CS SDO SCLK SDI
160 k
115 k
30 29 28 27 26 25 24 23 22 21 CF EPVSS2 EPN EPVDD EPP EPVSS1 AVSS PVDD CPIN VLDO 31 32 33 34 35 36 37 38 39 40 1 VBAT LVSS1 LSP LSVDD LSN 2 3 4 5 6 7 8 9 10 IOVDD MODE DVSS DVDD LSVSS2
1.425 V
90 k
DAC 3560C
16 15 14 13 12 11
SGND Fig. 4-5: Reference Pins: SREF, CF, SGND, VLDO
VLDO
CPIN
Fig. 4-3: PQFN40-1 package
AVSS
PVDD
Fig. 4-6: Supply Pins: CPIN, PVDD
HPVSS HPL HPR HPVDD SGND SREF HPCM AUXR AUXL AIN NC
VBAT
33 32 31 30 29 28 27 26 25 24 23 CF EPVSS2 EPN EPVDD EPP EPVSS1 AVSS PVDD CPIN VLDO (AVDD) NC 34 35 36 37 38 39 40 41 42 43 44 1 VBAT LSVSS1 LSP LSVDD LSN LSVSS2 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 NC NC RES CLI WSI DAI CS SDO SCLK SDI NC
P
100 Bypass
DAC 3560C
17 16 15 14 13 12
VLDO (AVDD) Fig. 4-7: Supply Pins: VLDO, VBAT
VLDO
NC IOVDD MODE DVSS DVDD
AUXL, AUXR, AIN SREF AVSS
Fig. 4-4: PMQFP44-1 package
Fig. 4-8: Input Pins: AUXL, AUXR, AIN
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PRELIMINARY DATA SHEET
DAC 3560C
HPVDD
DVSS SREF HPCM Fig. 4-13: Input/Output Pins: SDI, SCLK
HPVSS Fig. 4-9: Output Pin: HPCM
EPVDD
HPVDD
EPP EPN
EPVSS SREF HPL, HPR Fig. 4-14: Output Pins: EPP, EPN, EPVDD, EPVSS
HPVSS Fig. 4-10: Output Pins: HPL, HPR
LSVDD
LSP LSN IOVDD LSVSS Fig. 4-15: Output Pins: LSP, LSN, LSVDD, LSVSS DVSS Fig. 4-11: Input Pins: Mode, CS, DAI, WSI, CLI DVDD
IOVDD P N DVSS Fig. 4-12: Output Pin: SDO DVSS Fig. 4-16: Input pin RES
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DAC 3560C
4.6. Electrical Characteristics Abbreviations: tbd = to be defined vacant = not applicable positive current values mean current flowing into the chip
PRELIMINARY DATA SHEET
4.6.1. Absolute Maximum Ratings Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum rating conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. All voltages listed are referenced to ground (VSUP = 0 V) except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC.
Symbol
Parameter
Pin Name Min.
Limit Values Max. 852) 852)
Unit
TA1)
Ambient Operating Temperature PMQFP44-1 PQFN40-1 Case Operating Temperature - Operating Conditions: PMQFP44-1 PQFN40-1 Storage Temperature Maximum Power Dissipation PMQFP44-1 PQFN40-1 Supply Voltage VBAT, LSVDD, VLDO, HPVDD, EPVDD, CPIN, DVDD, IOVDD AIN, AUXL, AUXR, SREF, CF
-40 -40
C C
TC
-40 -40 -40
120 100 125 580 1100
C C C mW mW V
TS PMAX
VSUP
-0.3
6
VIana
Analog Input Voltages
-0.3
VLDO+0.3
V
1)
Measured on Micronas typical 2-layer (1s1p) board based on JESD - 51.2 Standard with maximum power consumption allowed for this package A power-optimized board layout is recommended. The Case Operating Temperature mentioned in the "Absolute Maximum Ratings" must not be exceeded at worst case conditions of the application.
2)
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PRELIMINARY DATA SHEET
DAC 3560C
Symbol
Parameter
Pin Name Min.
Limit Values Max. IOVDD+0.3
Unit
VIdig
Digital Input Voltages
MODE, SDO, SDI, SCLK, CS, DAI, WSI, CLI, RES SDI, SCLK
-0.3
V
VIRES VII2C IIana IIdig Analog Input Currents Digital Input Currents
-0.3 -0.3 -5 -5
DVDD+0.3 6 5 5
V V mA mA
AIN, AUXL, CF, AUXR, SREF, MODE, SDO, SDI, SCLK, CS, DAI, WSI, CLI, RES SDO, SDI, SCLK LDO HPL, HPR, HPCM EPN, EPP LSP, LSN
IOdig IOLDO IOHP IOEP IOLS
Digital Output Currents Analog Output Currents
-50 internally limited
50 50 internally limited
mA mA mA
tbd
tbd
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DAC 3560C
4.6.2.Recommended Operating Conditions
PRELIMINARY DATA SHEET
Functional operation of the device beyond those indicated in the "Recommended Operating Conditions/Characteristics" is not implied and may result in unpredictable behavior, reduce reliability and lifetime of the device. All voltages listed are referenced to ground (VSUP = 0 V) except where noted. All GND pins must be connected to a low-resistive ground plane close to the IC. Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. For power up/down sequences, see the instructions in Section 5.3.1.of this document.
4.6.2.1. General Recommended Operating Conditions Symbol Parameter Pin Name Min. TA Ambient Operating Temperature PMQFP44-1, PQFN40-1 - Operating Conditions - Extended Temperature Range:2) Case Operating Temperature PMQFP44-1 PQFN40-1 Analog Supply Voltage (Non-LDO mode) Charge pump: on Analog Supply Voltage (Non-LDO mode) Charge pump: off VSUPA2 VSUPD VSUPIO CLDOout CLDOin CPout CAin CSref
1)
Limit Values Typ. Max.
Unit
0 -40 0 0 VBAT, LSVDD, VLDO, HPVDD, EPVDD, CPIN 2.2
851) 85 105 95 3.4
C
TC
C C V
VSUPA1
2.7
5.5
V
Analog Supply Voltage (LDO mode) Digital Supply Voltage Digital Interface Voltage LDO Output Capacitor use Ceramic X7R, X5R LDO Input Capacitor Charge Pump Output Capacitor Analog Input Coupling Capacitor SREF Bypass Capacitor
VBAT, LSVDD DVDD IOVDD VLDO VBAT PVDD, VLDO AUXL, AUXR, AIN SREF
3 2.2 1.8 0.8 0.47 47 470 3.3 1.0
5.5 5.5 5.5 1.3
V V V F F nF nF F
A power-optimized board layout is recommended. The Case Operating Temperatures mentioned in the "Recommended Operating Conditions" must not be exceeded at worst case conditions of the application. Data sheet parameters are valid for "operating conditions" only. This product has been designed for and verified to the following temperature range: -40 C to +85 C. Design verification has been undertaken on silicon processed with a specialized parameter set in order to confirm robustness to standard production process variations.
2)
continued...
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PRELIMINARY DATA SHEET
DAC 3560C
Symbol
Parameter
Pin Name Min.
Limit Values Typ. 32 32 8 Max.
Unit
RLHP RLEP RLS
Headphone Load Resistance Earpiece Load Resistance Loudspeaker Load Resistance
HPL, HPR, HPCM EPP, EPN LSP, LSN
16 16 4

4.6.3. Characteristics (LDO Mode) Unless noted otherwise: LSVDD = VBAT = 3.6 V, EPVDD = HPVDD = CPIN = PVDD = VLDO = 2.85 V (LDO mode), TA = 0 C ... 85 C. Typical values are at TA = 25 C.
Symbol Parameter Pin Name Min. POWER MANAGEMENT, LDO VLDO VLDO LDO Output Voltage in Operational Mode LDO Output Voltage in Standby Mode VLDO 2.75 2.75 2.85 2.85 VBAT 2.95 2.95 V V V no load connected LDO not bypassed, no load connected LDO bypassed with internal 100 switch, no load connected LDO not bypassed LDO bypassed with internal 100 switch, no load connected Limit Values Typ. Max. Unit Test Conditions
VLDO
LDO Output Voltage in Zero Power Mode
HIGH-Z VBAT
V V
ILDO VDrop IShort
LDO Output Current LDO Drop Out Voltage LDO Short Circuit Current VBAT, VLDO VLDO 80 680
260
mA mV mA Iload = 100 mA VLDO = 0V, Standby or Operational Mode, LDO not bypassed Zero Power Mode Standby Mode, LDO bypassed, HPCM-Output enabled Standby Mode, LDO bypassed, HPCM-Output off Standby Mode, LDO on, HPCM-Output enabled Standby Mode, LDO on, HPCM-Output off Operational Mode
ISupTot
Supply Current
VBAT, LSVDD, VLDO, EPVDD, HPVDD, CPIN, PVDD, IOVDD, DVDD
10 170
A A
350 450 620 See Table 4-1. TTS HTS Thermal Shutdown Temperature Thermal Shutdown Hysteresis 130 145 20 160
A A A
C C
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DAC 3560C
PRELIMINARY DATA SHEET
Symbol
Parameter
Pin Name Min.
Limit Values Typ. Max.
Unit
Test Conditions
ANALOG AUDIO INPUTS - AIN, AUXL, AUXR VAI1 VAI2 RI 0 dB (Full Scale) Input Level Input Clipping Level Input Resistance 9 50 90 GAI dGAI EGAI Gain Setting Range Gain Step Size Gain Step Size Error -0.2 -20 2 0.2 AIN, AUXL, AUXR 2.04 2.85 12.5 69 125 16 83 155 20 dB dB dB Vpp Vpp k Gains set to 0 dB Gains set to -20 dB Gain = +20 dB Gain = 0 dB Gain = -20 dB
ANALOG AUDIO OUTPUTS - HEADPHONE, EARPIECE, LOUDSPEAKER GAO dGAO EGAO PHP PEP PLS IHPshort Volume Range Volume Step Size Volume Step Size Error Headphone Output Power Earpiece Output Power Loudspeaker Output Power Headphone Short-circuit Current HPL, HPR, (HPCM) EPP, EPN LSP, LSN HPL, HPR, HPCM, VLDO, AVSS EPP, EPN, VLDO, AVSS 0.1 -0.2 25 (22) 100 410 0.45 HPL, HPR, EPP, EPN, LSP, LSN -30 1.5 0.2 6 dB dB dB mW mW mW A THD < 0.1%, f=1 kHz, RL= 32 THD < 0.2%, f=1 kHz, RL= 32 (one channel) THD < 1%, f=1 kHz, RL= 8 not tested
IEPshort REFERENCES VREF1
Earpiece Short-circuit Current
0.15
0.5
A
not tested
Signal Reference Level
AIN, AUXL, AUXR HPL, HPR, HPCM, EPP, EPN derived from SREF LSP, LSN
1.425
V
SREF settled
VOREF2
Output Signal Reference Level
1.5
V
SREF settled
SIGNAL CHAINS - DYNAMIC PERFORMANCE Fsample = 48 kHz with 24-Bit data, Bandwidth = 20 Hz...22 kHz, Values in dB are unweighted, values in dBA are A-weighted. VAOHP VAOEP VAOLS 0 dB (full scale) Output Level Headphone 0 dB (full scale) Output Level Earpiece 0 dB (full scale) Output Level Loudspeaker HPL, HPR EPP, EPN, LSP, LSN 2.04 4.08 4.08 Vpp Vpp Vpp Gains, Volumes = 0 dB. No load connected. Gains, Volumes = 0 dB. No load connected. Gains, Volumes = 0 dB. No load connected.
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PRELIMINARY DATA SHEET
DAC 3560C
Symbol
Parameter
Pin Name Min.
Limit Values Typ. 98 94 99 95 99 95 Max.
Unit
Test Conditions
DRDA DRHP DRDA DREP DRDA DRLS DRAA DRHP
Dynamic Range, Digital to Analog Out
HPL, HPR, (HPCM) , EPP, EPN, LSP, LSN
dBA dB dBA dB dBA dB dBA dB dBA dB dBA dB dB dB dB
Digital to Headphone
Digital to Earpiece Digital to Loudspeaker Analog to Headphone, DAC off
Dynamic Range, Analog to Analog Out
DRAA DREP DRAA DRLS THDHP THDEP THDLS THD+N
AIN, AUXL, AUXR, HPL, HPR, HPCM, EPP, EPN, LSP, LSN
98 94 99 96 98 96
Analog to Earpiece, DAC and headphone off Analog to Loudspeaker, DAC and headphone off Headphone, RL = 32 , POUT = 15 mW Earpiece, RL = 32 , POUT = 50 mW Loudspeaker, RL = 8 , POUT = 200 mW Headphone, volumes muted, Earpiece, Loudspeaker Crosstalk Headphone to Loudspeaker Crosstalk Earpiece to Loudspeaker Crosstalk Loudspeaker to Earpiece Crosstalk Headphone left right, single-ending mode Headphone, f = 1 kHz, VBAT > 3 V, including LDO-Isolation VRIPPLE,peak = 0.25 V Zero-Audio Signal Earpiece, f = 1 kHz, VBAT > 3 V, including LDO-Isolation VRIPPLE,peak = 0.25 V Zero-Audio Signal Loudspeaker, f = 1 kHz, VBAT > 3 V VRIPPLE,peak = 0.25 V Zero-Audio Signal
HPL, HPR, (HPCM) EPP, EPN LSP, LSN
-76 (-68) -69 -63
LM
Mute Level
HPL, HPR, (HPCM), EPP, EPN, LSP, LSN HPL, HPR, LSP, LSN EPP, EPN, LSP, LSN LSP, LSN, EPP, EPN, HPL, HPR,
-105
dB
XTALKHPLS
Crosstalk
-115
-95
dB
XTALKEPLS
Crosstalk
-110
-95
dB
XTALKLSEP
Crosstalk
-110
-95
dB
XTALKHP
LR
Crosstalk
-90
-80
dB
PSRRHP
PSRR
VBAT, HPL, HPR, (HPCM)
100
115
dB
PSRREP
PSRR
VBAT, EPP, EPN
100
110
dB
PSRRLS
PSRR
VBAT, LSP, LSN
80
95
dB
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DAC 3560C
4.6.4. Characteristics (Non-LDO Mode)
PRELIMINARY DATA SHEET
Unless noted otherwise: LSVDD = VBAT = EPVDD = HPVDD = CPIN = VLDO = 2.2 V to 5.5 V (Non-LDO mode), TA = 0 C to 85 C. Typical values are at TA = 25 C.
Symbol Parameter Pin Name Min. POWER MANAGEMENT, LDO ISupTot Supply Current at 2.2 V VBAT, LSVDD, VLDO, EPVDD, HPVDD, CPIN, PVDD, IOVDD, DVDD 10 185 355 A A A Zero Power Mode Standby Mode, HPCMOutput enabled Standby Mode, HPCMOutput off Limit Values Typ. Max. Unit Test Conditions
ISupTot
Supply Current at 5 V 235 420
10
A A A
Zero Power Mode Standby Mode, HPCMOutput enabled Standby Mode, HPCMOutput off
ANALOG AUDIO INPUTS - AIN, AUXL, AUXR VAI1 VAI2 0 dB (Full Scale) Input Level Input Clipping Level AIN, AUXL, AUXR 0.715 x VLDO VLDO Vpp Vpp Gains set to 0 dB Gains set to -20 dB
ANALOG AUDIO OUTPUTS - HEADPHONE, EARPIECE, LOUDSPEAKER PHP PEP PLS PHP PEP PLS REFERENCES VOREF1 Output Signal Reference Level HPL, HPR, HPCM, EPP, EPN derived from SREF LSP, LSN VLDO/2 V SREF settled Headphone Output Power at 2.2 V Earpiece Output Power at 2.2 V Loudspeaker Output Power at 2.2 V Headphone Output Power at 5 V Earpiece Output Power at 5 V Loudspeaker Output Power at 5 V HPL, HPR, (HPCM) EPP, EPN LSP, LSN HPL, HPR, (HPCM) EPP, EPN LSP, LSN 12 50 170 78 300 1.1 mW mW mW mW mW W THD < 0.1%, f=1 kHz, RL= 32 THD < 0.2%, f=1 kHz, RL= 32 THD < 1%, f=1 kHz, RL= 8 THD < 0.1%, f=1 kHz, RL= 32 THD < 0.2%, f=1 kHz, RL= 32 THD < 1%, f=1 kHz, RL= 8
VOREF2
Output Signal Reference Level
VLDO/2
V
SREF settled
SIGNAL CHAINS - DYNAMIC PERFORMANCE Fsample = 48 kHz with 24-Bit data, Bandwidth = 20 Hz...22 kHz, Values in dB are unweighted, values in dBA are A-weighted. VAOHP 0 dB (Full scale) Output Level Headphone HPL, HPR 0.715 x VLDO Vpp Gains, Volumes = 0 dB. No load connected.
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PRELIMINARY DATA SHEET
DAC 3560C
Symbol
Parameter
Pin Name Min.
Limit Values Typ. 1.43 x VLDO 1.43 x VLDO 96 93 98 94 98 94 Max.
Unit
Test Conditions
VAOEP VAOLS DRDA DRHP DRDA DREP DRDA DRLS DRDA DRHP DRDA DREP DRDA DRLS DRAA DRHP DRAA DREP DRAA DRLS DRAA DRHP DRAA DREP DRAA DRLS THDHP THDHP THDEP THDLS
0 dB (Full scale) Output Level Earpiece 0 dB (Full scale) Output Level Loudspeaker Dynamic Range, Digital to Analog Out at 2.2 V
EPP, EPN, LSP, LSN HPL, HPR, (HPCM), EPP, EPN, LSP, LSN
Vpp Vpp dBA dB dBA dB dBA dB dBA dB dBA dB dBA dB dBA dB dBA dB dBA dB dBA dB dBA dB dBA dB dB dB dB dB
Gains, Volumes = 0 dB. No load connected. Gains, Volumes = 0 dB. No load connected. Digital to Headphone Digital to Earpiece Digital to Loudspeaker Digital to Headphone Digital to Earpiece Digital to Loudspeaker Analog to Headphone, DAC off Analog to Earpiece, DAC and headphone off Analog to Loudspeaker, DAC and headphone off Analog to Headphone, DAC off Analog to Earpiece, DAC and headphone off Analog to Loudspeaker, DAC and headphone off Headphone, RL= 32 , POUT = 8 mW Headphone + HPCM, RL= 32 , POUT = 8 mW Earpiece, RL= 32 , POUT = 30 mW Loudspeaker, RL=8 , POUT = 130 mW Headphone, RL= 32 , POUT = 50 mW Headphone + HPCM, RL= 32 , POUT = 50 mW Earpiece, RL= 32 , POUT = 140 mW Loudspeaker, RL=8 , POUT = 600 mW Headphone, f = 1 kHz, Earpiece, f = 1 kHz Loudspeaker, f = 1 kHz
Dynamic Range, Digital to Analog Out at 5 V
103 99 102 98 94 91
Dynamic Range, Analog to Analog Out at 2.2 V
AIN, AUXL, AUXR, HPL, HPR, HPCM, EPP, EPN, LSP, LSN
96 92 98 94 95 92
Dynamic Range, Analog to Analog Out at 5 V
104 100 103 99 94 91
THD+N at 2.2 V
HPL, HPR HPL, HPR, (HPCM) EPP, EPN LSP, LSN
-71 -67 -69 -62
THDHP THDHP THDEP THDLS
THD+N at 5 V
HPL, HPR HPL, HPR, (HPCM) EPP, EPN LSP, LSN
-82 -74 -76 -63
dB dB dB dB
PSRRHP PSRREP PSRRLS
PSRR
VBAT, HPL, HPR, (HPCM) VBAT, EPP, EPN VBAT, LSP, LSN
68 70 70
dB dB dB
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DAC 3560C
4.6.5. Terminology 1. THD+N (dB): Total Harmonic Distortion+Noise: the ratio of the RMS values of Distortion+Noise within a certain bandwidth to the fundamental signal at a given output level or output power. 2. DR (dB): Dynamic Range: a measure of the difference between the highest and lowest part of a signal. Normally, it is a THD+N measurement with a sinusoidal input signal at a level of 60 dB below full scale. Adding the 60 dB to the result represents the dynamic range, for example: THD+N at -60 dB = -35 dB, DR = 95 dB. 3. XTALK (dB) : Crosstalk : applying a full-scale signal to one input channel, while measuring every inactive input or output channel.
PRELIMINARY DATA SHEET
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PRELIMINARY DATA SHEET
DAC 3560C
4.6.6. Digital Characteristics 4.6.6.1. I2C Bus Characteristics
Symbol Parameter Pin Name Min. VI2CIL VI2CIH tI2C1 tI2C2 tI2C5 tI2C6 tI2C3 tI2C4 fI2C VI2COL II2COH tI2COL1 tI2COL2 I2C BUS Input Low Voltage I2C BUS Input High Voltage I C START Condition Setup Time I2C STOP Condition Setup Time I2C Data Setup Time before Rising Edge of Clock I2C Data Hold Time after Falling Edge of Clock I2C Clock Low Pulse Time I2C Clock High Pulse Time I C BUS Frequency I2C Data Output Low Voltage I2C Data Output High Leakage Current I2C Data Output Hold Time after Falling Edge of Clock I2C Data Output Setup Time before Rising Edge of Clock 15 SCLK, SDI
2 2
Limit Values Typ. Max. 0.3 0.65 120 120 55
Unit
Test Conditions
SCLK, SDI
IOVDD IOVDD ns ns ns
55
ns
SCLK
500 500 1.0 0.4 1.0
ns ns MHz V A II2COL = 3 mA VI2COH = 5 V
ns
100
ns
fI2C = 1 MHz
1/FI2C SCLK TI2C4 TI2C3
TI2C1 SDI as input
TI2C5
TI2C6
TI2C2
TI2COL2 SDI as output
TI2COL1
Fig. 4-17: I2C bus timing diagram
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DAC 3560C
4.6.6.2. I2S Bus Characteristics
Symbol VI2SIL VI2SIH ZI2SI ILEAKI2S tI2S1 tI2S2 RCLI FCLI Parameter Input Low Voltage Input High Voltage Input Impedance Input Leakage Current I S Input Setup Time before Rising Edge of CLI I2S Input Hold Time after Rising Edge of CLI I2S Clock Input Ratio I2S Clock Frequency CLI,DAI
2
PRELIMINARY DATA SHEET
Pin Name DAI CLI WSI
Min.
Typ.
Max. 0.2
Unit IOVDD IOVDD
Test Conditions
0.65 5 -1 1
pF A ns 0 V < UINPUT < IOVDD for details see Fig. 4-18 ( I2S interface)
DAI WSI
10
20
ns
0.9
1.1 12.3 MHz 32 bit, Fsample = 192 kHz
1/FI2SWS WSI
SONY format PHILIPS format
SONY format PHILIPS format Detail A
CLI
DAI
R LSB L MSB
L LSB R MSB
R LSB L LSB
16 bit left channel
16 bit right channel
Detail A
CLI
TI2S1
TI2S2
DAI/WSI
Fig. 4-18: I2S timing diagram
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PRELIMINARY DATA SHEET
DAC 3560C
4.6.6.3. Reset Input Characteristics
Symbol Parameter Pin Name Min. VIRES VIRES ZIRES IRES Input Low Voltage Input High Voltage Input Impedance Input Leakage Current -1 RES 0.65 5 1 Limit Values Typ. Max. 0.2 DVDD DVDD pF A 0 V < UINPUT < DVDD Unit Test Conditions
4.6.6.4. Mode Input Characteristics
Symbol Parameter Pin Name Min. VIMODE VIMODE ZIMODE IIMODE Input Low Voltage Input High Voltage Input Impedance Input Leakage Current -1 MODE 0.65 5 1 Limit Values Typ. Max. 0.2 IOVDD IOVDD pF A 0 V < UINPUT < IOVDD Unit Test Conditions
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DAC 3560C
4.6.6.5. SPI-Bus Characteristics
Symbol Parameter Pin Name Min. VSPIIL VSPIIH ZSPII ILEAKSPI tSPI1 tSPI2 RCLI VSPIOL VSPIOH fSCLK1 Input Low Voltage Input High Voltage Input Impedance Input Leakage Current SPI Input Setup Time before Rising Edge of SCLK SPI Input Hold Time after Rising Edge of SCLK SPI Clock Input Ratio SPI Output Low Voltage SDO SDI CS 40 -1 10 SDI SCLK CS 5 1 0.65 Limit Values Typ. Max. 0.2
PRELIMINARY DATA SHEET
Unit
Test Conditions
IOVDD IOVDD pF A ns 0 V < UINPUT< IOVDD
ns
0.9
1.1 0.4 V ISPIOL = 0.5 mA, IOVDD= 1.8 V ISPIOH = -0.5 mA IOVDD = 1.8 V CL = 20 pF, IOVDD = 3.3 V CL = 20 pF, IOVDD = 1.8 V CL = 20 pF, IOVDD = 3.3 V CL = 20 pF, IOVDD = 1.8 V
SPI Output High Voltage
1.2
V
SPI Clock Frequency, read access
SCLK, SDI, SDO
10 6
MHz MHz MHz MHz
fSCLK2
SPI Clock Frequency, write access
SCLK, SDI t
10 6
CS tSPI1 tSPI2
SCLK tSPI1 tSPI2 SDI
(MSB) RW = 1 A4 A3 A2 A1 A0 (LSB) D7 (MSB) D6... ..D1 . D0 (LSB)
Address Byte
Data Byte
SDO
tristate
1. SPI write access
CS tSPI1 tSPI2
SCLK tSPI1 tSPI2 SDI
tristate RW = 0 A4 A3 A2 A1 A0 ignored ignored
SDO
2. SPI read access
D7
D6... ...D1
D0
tristate
Fig. 4-19: SPI write and read access
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PRELIMINARY DATA SHEET
DAC 3560C
4.6.7. Power Consumption (LDO Mode) LSVDD=VBAT= 3.6 V, EPVDD=HPVDD=CPIN=PVDD=VLDO= 2.85 V, DVDD = 2.2 V, IOVDD = 1.8 V. Typical Values, Operational Mode. Table 4-1: Current Consumption Examples (Operational Mode) Control Bits SMM PDAC PAIN PAUX PL PEP PRH PLH ENHPC Current Consumption Analog 1) DVDD 2) IOVDD 2) 7.5 0.7 < 10 8.7 4.3 0.3 4.7 3.1 0 3.4 0 6.1 0 7.3 0 13 0.7 X X X X X X X X X X X X X X X X A B C X X D X X X X X X E X F X X X X X X X X X G H I Description Select mono mode Power DAC Power AIN input Power AUX input Power Loudspeaker Power Earpiece Power Right Headphone Power Left Headphone Enable Headphone Common Driver Unit mA mA A
All figures are quiescent currents with zero audio signal, no load connected.
1) Including all analog supply pins: VBAT, LSVDD, VLDO, EPVDD, HPVDD, CPIN, PVDD 2) I2S digital audio data received with f sample = 48 kHz, 32-bit word length, CLI=3.072 MHz.
A) Stereo D/A Headphone L/R B) Stereo D/A Headphone L/R + Headphone Common C) Mono D/A Loudspeaker D) Mono D/A Earpiece E) AIN Loudspeaker F) AIN Earpiece G) AUX Headphone L/R H) AUX Headphone L/R + Headphone Common I) All signal chains on, stereo mode
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DAC 3560C
5. Detailed Mode Description The DAC 3560C features many modes of operation, which can be set for a targeted application using the internal registers. Also, some external components and pin-to-pin connections may differ from application to application - mainly depending on whether the internal LDO is used or not. A detailed description of these features is given below.
PRELIMINARY DATA SHEET
The LDO output can be bypassed using the BYPLDOFunction bit in the MODE Control Register. Selecting this bit closes an internal 100 switch between the LDOs input and output pin. This function is only available in Zero Power and Standby Mode. The LDO is then turned off. Use this function to reduce the quiescent current in Standby Mode.
5.2. Non-LDO Mode, Using the DAC 3560C without the LDO 5.1. LDO Mode, Using the internal Low-Dropout Regulator The SNLDOM-Function bit in the MODE Control Register controls the operation of the DAC 3560C with, or without, use of the internal LDO. The default setting selects the LDO mode. The LDO then delivers a stable 2.85 V at its output when the device is in Standby or Operational Mode. The signal reference level for the audio outputs is 1.425 V (Pin SREF) except for the loudspeaker output, which has a reference level of 1.5 V. The LDO is intended to supply the headphone and the earpiece driver. Connect the supply pins of these drivers (HPVDD, EPVDD) to the LDO output (VLDO). Also connect the pins from the charge pump (CPIN, PVDD) to the LDO output. The charge pump is disabled when the DAC 3560C is in LDO Mode. Using the LDO increases the PSRR of the headphone and earpiece outputs in respect to the battery line (VBAT) to more than 100 dB. The input voltage range for full performance of the LDO is 5.5 V to 3.0 V. Lowering the input voltage further will - depending on load - reduce the PSRR until the LDO is out of regulation. Selecting the SNLDOM-Function Bit in the MODE Control Register disables the LDO and configures the DAC 3560C for a supply voltage range from 2.2 V to 5.5 V. The signal reference level for the audio outputs is formed by a resistive voltage divider to VBAT/2. A second filter capacitor can be connected to pin CF to form a second order noise filter. Connect the LDO output pin (VLDO) directly to the battery line (VBAT) as well as the supply pins of the audio drivers (HPVDD EPVDD, LSVDD) and the charge pump input (CPIN). When using the LDO, connect a 1 F ceramic capacitor (X7R, X5R) to the LDO output to ensure a stable operation of the LDO. The DAC 3560C uses an internal charge pump circuit to keep internal circuits operating at low supply voltages. The charge pump must be used if the supply voltage at VBAT is below 2.7 V. Connect an additional capacitor between pin PVDD and pin VLDO to allow the internal charge pump to work properly.
EPVDD
HPVDD PVDD DAC 3560C
EPVDD LSVDD
HPVDD PVDD
2.2V...5.5V
LSVDD
Bypass Switch
VBAT
VLDO
3 V...5.5 V
VBAT
VLDO LDO CPIN DAC 3560C 1 F (X7R 90 k
VBAT/2 SREF CF
2.85 V
CPIN
160 k 115 k
1.425 V
SREF CF
160 k 115 k 1.425 V (Reference Block)
90 k
LSVSS
AVSS
SGND
EPVSS HPVSS
LSVSS
AVSS
SGND
EPVSS HPVSS
Fig. 5-1: Simplified application diagram using the DAC 3560C in LDO-Mode
Fig. 5-2: Simplified application diagram using the DAC 3560C in Non-LDO-Mode
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PRELIMINARY DATA SHEET
DAC 3560C
Selecting the SMM-Function Bit in the MODE Control Register configures the DAC 3560C for mono or stereo operation. Selecting mono mode will turn off the right DAC-channel. The I2S audio data format is still the same as for stereo operation but right channel audio data are dropped internally. The right headphone driver will be routed to the left signal chain. Use the Mono Mode to reduce the current consumption if no stereo signal processing is required. For both modes, stereo or mono, the DAC 3560C supports side tone mixing from the auxiliary inputs (AUXL, AUXR, AIN). It is also possible to use the DAC 3560C without digital audio from the DAC, if only an analog-in to analog-out function is needed. See Table 5-1 for side tone capabilities of the DAC 3560C. Please also refer to the functional block diagram (see Fig. 1-1 on page 5), to see how audio signals are mixed.
5.3. Headphone Common Driver The DAC 3560C has driver outputs for earpiece, loudspeaker and headphone connection. While the earpiece and loudspeaker outputs are of the differential type, the headphone driver outputs are single-ended. Single-ended drivers usually require a large coupling capacitor to block the DC bias from the headphone. The DAC 3560C provides a headphone common output (HPCM), which eliminates the need for bulky DCblocking capacitors. Selecting the ENHPC-Bit in the BLOCK Control Register enables the headphone common driver output (HPCM). The HPCM-driver is then turned on with the left or right headphone and delivers the audio signal reference level at the output (1.425 V or VLDO/2). Capacitive coupling is also possible for all driver outputs. Make sure that the ENHPC-Bit in the BLOCK Control Register is set correctly before setting the device in Standby or Operational Mode, otherwise the DAC 3560C might fail to bias DC-blocking capacitors at the headphone outputs.
Table 5-1: Mixing Possibilities: All Audio Inputs/ Outputs active. Volumes, Gains set to 0 dB Output
LSP Loudspeaker LSN DAC 3560C HPCM HPL Headphone L
Stereo Mode
Ain + AuxL +DacL Ain + AuxR +DacR Ain +(AuxL+AuxR)/2 +(DacL+DacR)/2 Ain +(AuxL+AuxR)/2 +(DacL+DacR)/2
Mono Mode
Ain +(AuxL+AuxR)/2 + DacL Ain +(AuxL+AuxR)/2 + DacL Ain +(AuxL+AuxR)/2 + DacL Ain +(AuxL+AuxR)/2 + DacL
Left Headphone Output Right Headphone Output Loudspeaker Output Earpiece Output
1.425V or VLDO/2
EPP Earpiece EPN HPR
Headphone R
Fig. 5-3: Headphone connection, using the headphone common driver output
EPP
HPL
Note: Please note that the sum of all input signals (DAC, AUX, AUXR, AIN), must not exceed the 0 db (Full Scale Level), otherwise signal degradation will occur due to clipping.
EPN DAC 3560C LSP HPR LSN
Fig. 5-4: Headphone connection by capacitive coupling
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DAC 3560C
5.3.1. Digital Supply The DAC 3560C has two supply pins for the digital part of the IC. The IOVDD Pin supplies the digital I/O cells, except the RES input. The usable voltage range is 1.8 V to 5.5 V, allowing direct connection to modern microcontrollers. Pin DVDD supplies the internal digital core of the IC and the RES input (see Fig. 4-16 on page 21) and (see Fig. 6-1 on page 39) Application Circuit. Make sure that DVDD is always available first or simultaneously with the other supply lines, in order to allow a proper reset. Do not connect IOVDD or DVDD to the LDO-Output when using the LDO, as this will result in a deadlock situation for the DAC 3560C.
PRELIMINARY DATA SHEET
After releasing the RES pin, it is possible to program all registers of the DAC 3560C. However, all register contents are suppressed except the BYPLDO-function bit from the Mode Control Register, which allows bypassing the LDO output with an internal 100 switch to VBAT. The following bits: - SNLDOM: (For using the device with or without the LDO) - ENHPC: (For using or not using the headphone common driver) should be set before entering the next power state (Standby Mode).
5.3.2. Power On/Off Sequence The DAC 3560C has three power states - Zero Power, Standby and Operational Mode, that permit powering on the device without clicks and pops, while giving the lowest current consumption possible. The power states of the DAC 3560C are controlled by function bits PM[1:0] in the Mode Control Register, selectable via the I2C/SPI control interface.
Standby Mode: In Standby Mode, external capacitors are biased to their DC level (signal reference level). Only circuitries to bias the external capacitors are enabled, resulting in a low-current consumption. Allow the signal reference level (Pin SREF, CF) to settle before changing to Operational Mode. If the LDO is enabled (bit SNLDOM=0) it delivers a stable 2.85 V at the output (VLDO). Bypassing the LDO with an internal 100 switch to VBAT is also possible. The LDO is then disabled. Use this function to reduce the quiescent current in Standby Mode. All registers are programmable during Standby Mode, but the content of the Block Control register is suppressed. It is recommended to keep all output volumes in their mute position before changing to Operational Mode in order to avoid audible clicks and pops.
Battery Insertion Reset
SPI/I2Ccommand
Operational Mode: Selected signal chains are active SPI/I2Ccommand
Zero Power mode: All blocks are off
SPI/I2Ccommand
Standby Mode: External capacitors are biased to their DC-level
Fig. 5-5: Power states
Operational Mode: In Operational Mode, the content of the Block Control register will become transparent, so that all selected blocks and their signal chains are active. Programming all registers is possible allowing changing signal paths on the fly. However, it is recommended to ramp down the output volumes before, in order to avoid audible clicks and pops.
Zero Power Mode: When the battery voltage is initially applied, the DAC 3560C must be reset with a low signal at Pin RES, in order to clear all internal registers to their default values, which sets the DAC 3560C into a defined state (Zero Power Mode). In Zero Power Mode, all blocks are forced off and the current consumption of the device is zero.
Power-Down Sequence: Powering down the DAC 3560C from Operational Mode or Standby Mode can be achieved by selecting Zero Power Mode from the Mode Register. All register values remain unchanged. It is possible to clear all register values to their default values by a write access to the RESET Register.
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6. Application Circuit
3.0 to 5.0 V VCC1 Loudspeaker > 4 Ohm 1 2 Earpiece > 16 Ohm 1 2
GND DGND
SGND AGND Starting Point for DGND
VLDO CPIN PVDD AVSS EPVSS1 EPP EPVDD EPN EPVSS2 CF
44 43 42 41 40 39 38 37 36 35 34
N.C. VLDO CPIN PVDD AVSS EPVSS1 EPP EPVDD EPN EPVSS2 CF
AGND
DGND
N.C. SDI SCLK SDO CS DAI WSI CLI RESQ N.C. N.C.
12 13 14 15 16 17 18 19 20 21 22
SDI SCLK SDO L.V. DAI WSI CLI PORQ
DGND 1 VBAT LSVSS1 2 3 LSP LSVDD 4 LSN 5 LSVSS2 6 DVDD 7 DVSS 8 MODE 9 IOVDD 10 VBAT LSVSS1 LSP LSVDD LSN LSVSS2 DVDD DVSS MODE IOVDD
VLDO CPIN PVDD AVSS EPVSS1 EPP EPVDD EPN EPVSS2 CF
PCM source -Controller GSM-module MIDI Decoder (MAS 35x5G) MP3 Decoder (MAS 35x9F)
10k PORQ 1nF
40 39 38 37 36 35 34 33 32 31
VLDO CPIN PVDD AVSS EPVSS1 EPP EPVDD EPN EPVSS2 CF
DAI WSI CLI
11 12 13 14 15 16 17 18 19 20
SDI SCLK SDO CS DAI WSI CLI RES N.C. N.C.
SDI SCLK SDO CS DAI WSI CLI PORQ NC1 NC2
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Sept. 8, 2004; 6251-588-2PD
PRELIMINARY DATA SHEET
wide copper lines
470 nF + AGND
1uF ceramic X7R, X5R AGND
AGND Starting Point for SGND Headphone > 16 Ohm 100nF + 3.3 uF 33 32 31 30 29 28 27 26 25 24 23 SREF SGND HPVDD HPR HPL HPVSS HPCM AUXR AUXL AIN
10uF (optional)
2.2 to 3.6 V VCC2 MODE
VBAT 1 LSVSS1 2 LSP 3 LSVDD 4 LSN 5 LSVSS2 6 DVDD 7 DVSS 8 9 MODE IOVDD 10 11
VBAT LSVSS1 LSP LSVDD LSN LSVSS2 DVDD DVSS MODE IOVDD N.C.
Micronas DAC 3560C (PMQFP44)
SREF SGND HPVDD HPR HPL HPVSS HPCM AUXR AUXL AIN N.C.
SGND AUX Stereo 470 nF 470 nF AIN Mono 470 nF
DAC 3560C (PQFP44) NC2 NC1 AGND AGND
4.7 k
4.7k
I2CC I2CD
SREF SGND HPVDD HPR Micronas DAC 3560C HPL (QFN40) HPVSS HPCM AUXR AUXL AIN
30 29 28 27 26 25 24 23 22 21
SREF SGND HPVDD HPR HPL HPVSS HPCM AUXR AUXL AIN
DAC 3560C (QFN40)
DAC 3560C
Fig. 6-1: Application circuit in LDO Mode, I2C Control
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DAC 3560C
6.1. Suggestions for System Debugging The goal of designing a bug-free system requires a systematic approach. One important task is to prepare the right test points, so that debugging is easier or possible at all. If the chosen package is of the BGA- or QFN-type, the suggestions here become strong rules. The signals listed below represent the most important interface and power signals. They must be connected to test points on the circuit board, which allow the measurement with at least an oscilloscope's probe. DVDD, IOVDD, HPVDD, EPVDD, LSVDD, PVDD, VLDO, SREF MODE, CS Some signals, such as I2C Control bus or digital Audio I2S bus, must be equipped with solderable points or routed to connectors, so that a protocol can be analyzed. SCLK, SDI, SDO CLI, WSI, DAI The RESET pin of a chip plays an important role, especially its rising edge timing-position in relation to the rising of the VDD. The possibility to detach it from the board and provide a different timing for test purposes can lead to fast debug results. RES Micronas encourages every system designer to take advantage of our experience.
PRELIMINARY DATA SHEET
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PRELIMINARY DATA SHEET
DAC 3560C
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DAC 3560C
7. Data Sheet History 1. Preliminary Data Sheet: "DAC 3560C Audio-Subsystem for Portable Applications", May 7, 2004, 6251-588-1PD. First release of the preliminary data sheet. Major changes: - Specification for PMQFP44-1 package added. - New package diagrams for PMQFP44-1 and PQFN40-1 - Correction in application circuit. 2. Preliminary Data Sheet: "DAC 3560C Audio-Subsystem for Portable Applications", Sept. 8, 2004, 6251-588-2PD. Second release of the preliminary data sheet. Major changes: - Section 4.6. "Electrical Characteristics" corrected - Section 6.1. "Suggestions for System Debugging" added
PRELIMINARY DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-588-2PD
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
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